The ongoing reduction in size of electronic device elements, particularly memory devices, has led to the development of DRAM cells in which a typical cell comprises a transistor connected to a trench capacitor (that is, a capacitor formed in a trench etched into the substrate so as to consume minimal substrate surface area). Trench capacitors generally have an insulator (usually nitride or oxynitride) on the bottom and adjacent sidewalls of the trench serving as the capacitor dielectric, and regions of conductive doped polysilicon filling the trench serving as the capacitor plates or nodes.
Steps in a conventional process for forming a trench capacitor are shown in FIGS. 1A–1H. A trench 10 is etched into the substrate 1 (FIG. 1A); at this point in the overall device fabrication process, the substrate surface 5 is typically covered by a pad insulator 2 such as silicon nitride. A node dielectric 3 is deposited on the sidewalls and bottom of the trench and on top of the pad insulator 2. A layer of polysilicon 21 is deposited on this dielectric, thereby covering the top surface 11 of the pad insulator and filling the trench. The polysilicon is etched so that it is recessed in the trench; the node dielectric 3 is then removed from the top surface 11 and the upper sidewall 12 of the trench. The recessed polysilicon (forming a node at the bottom of the trench) and node dielectric thus appear as shown in FIG. 1B. Another dielectric layer 4 (typically oxide) is deposited on the top surface 11, the trench sidewalls 12 and the top surface 26 of the node polysilicon; this layer is etched so as to leave a collar in the interior of the trench on the upper sidewalls 12 (FIG. 1C). A second polysilicon deposition is performed to fill the trench and cover the surface 11; this polysilicon 22 is then polished (typically by chemical-mechanical polishing or CMP) so that it is coplanar with surface 11 (FIG. 1D). Polysilicon 22 is subsequently etched so that it is recessed in the trench (FIG. 1E). The collar 4 is then etched so that the top portion of the trench sidewall is again exposed (FIG. 1F). A third polysilicon deposition is performed, followed by planarization (FIG. 1G) and another etch process so that polysilicon 23 is recessed below the substrate surface 5 (FIG. 1H).
The trench capacitor structure 30 is subsequently covered at its top surface 25 by the shallow trench isolation (STI) 40, which also overlaps a portion of the trench capacitor as shown in FIG. 2. A CMOS transistor 50 having gate 51, source 52 and drain 53 is formed adjacent to the trench capacitor. A buried strap region 55 (formed by diffusion of dopants from polysilicon 22) connects the source 52 with polysilicon 23. The junction between polysilicon 23 and the buried strap 55 is called the buried strap junction. The collar 4 serves to prevent charge leakage from the capacitor at the buried strap junction.
As outlined above, the conventional process for forming a trench capacitor requires three polysilicon deposition steps, three polysilicon recess steps, and at least two planarization steps. This is a complicated and costly process, particularly with present-day 300 mm diameter substrates. The depositions typically are performed in a furnace and require long process times; the CMP planarization presents significant process control challenges when 300 mm substrates are used. In addition, the formation of three polysilicon regions 21, 22, 23 in the trench capacitor creates two polysilicon/polysilicon interfaces 31, 32 within the trench, resulting in increased internal resistance in the polysilicon; an increase in polysilicon resistance will in turn reduce device speed. There is a need for a trench capacitor formation process which requires fewer steps and can be practiced at lower cost, and preferably provides improved device performance.